The monitoring of gate oxides is a difficult but highly desirable procedure for reducing manufacturing rejects in the semiconductor industry. On one hand, accuracy is required to ensure that good chips are not wrongly rejected and defective chips are not mistakenly passed by; on the other hand, the monitoring cannot be time consuming, so as not to hold up the throughput.
In the manufacture of semiconductor devices, various layers of material are deposited on the semiconductor substrate followed by removal of unwanted portions of each layer. The procedures used to deposit the layers, such as chemical vapor deposition in sputtering conditions, as well as the procedures used to remove unwanted material, such as such as chemical, plasma, or reactive ion etching among others, may cause damage to underlying structures, particularly very thin structures, such as gate oxides.
For example, metal-oxide semiconductor (MOS) transistors rely upon a thin silicon oxide gate separating the gate from the channel. Damage to the gate oxide layer may result in unacceptable current leakage from the gate to the channel, thereby resulting in reduced device performance or even total failure.
The manufacturer would therefore desire to test and monitor the quality of the gates coming down the assembly line so as to detect faults in the manufacturing process and to remove defective chips before further processing and packaging wasted upon them.
One conventional way for testing the dielectric layer is named Time Dependent Dielectric Breakdown (TDDB), which is to estimate the characteristic and the lifetime of the dielectric layers of the chips being made of the same wafer (i.e., in the wafer level). However, TDDB requires longer testing time, and particularly needs to test multiple test structures for obtaining enough amount of testing samples.
Another conventional way for testing the dielectric layer is Ramped Voltage Breakdown Test. Typically, a ramped sweep voltage is placed across the gate oxide by connecting probes to the gate and the semiconductor substrate, just beneath the gate oxide. A typical procedure would be to ramp the voltage from a base voltage to an increasingly higher stress voltage and take two current measurements, one at the base voltage and one at the stress voltage. This procedure is repeated, increasing the stress voltage each time in some small increment until a maximum stress voltage is reached. The procedure is accurate enough, but still time consuming.
Furthermore, for semiconductor memory devices, like SRAM, one skilled in the art would appreciate that the value of the lowest operating voltage (Vccmin) may be dependent on the process used to fabricate the memory array or design of the memory. However, those TDDB test and Ramped Voltage Breakdown Test mentioned above, as well as other conventional wafer level testing, cannot reflect the shift of Vccmin, which can only be investigated at the test in the product level, e.g., Accelerated High Temperature Operation Life (AHTOL). But it will be too late and will waste a lot of resource if the test result is not satisfied.
Therefore, it is desired to have a method for quickly testing gate dielectric of semiconductor devices in wafer level. It will be beneficial if the testing method can provide a new indication of defects of the semiconductor devices. It will be more advantageous if the testing method, performed in the wafer level, can reflect the shift of Vccmin mentioned above.